Fabrication of organic flip chip electronic modules typically includes a chip join reflow on a laminate, such as a thin-laminate organic circuit board, for example, a printed wiring board (PWB) or printed circuit board (PCB). During fabrication of an organic flip chip electronic module, particularly those modules using thin core and coreless organic laminates, it is important that the laminate remain as flat as possible in the chip site area during a chip join reflow. Failure to keep the laminate flat can result in undesirable solder bridging (that is, shorts), as well as chip interconnect opens. Undesirable die stresses can also result from variations in the laminate shape during reflow. Undesirable laminate warpage can also occur during processing of a chip/die and a laminate, for example, during flip chip fabrication which can present itself in a variety of shapes and each shape can affect the process in a different way. Die stresses can manifest themselves as a cracked die, or separations of the dielectric layers within the die (e.g., typically, white bumps). Increased laminate warpage (also referred to as warping) during die reflow can also lead to increased module warpage at the end of a bond and assembly process, which can cause the module to fail final co-planarity specifications. Laminates can have varying shapes depending on their location within the panel prior to dicing, which can lead to varying results after chip join reflow if there are no provisions to compensate for the laminate warpage.
Laminate warpage or warping may be defined by the laminate's curvature from a flat surface of the bottom of the laminate. Alternatively, laminate warpage may be defined by a planar surface mating with the bottom of the laminate, thereby providing a horizontal plane to reference any warping of the laminate.
Previous attempt to alleviate the problem of laminate warpage during processing, for example, during flip chip electronic module processing, includes using: A) Copper balancing methods in the substrate design, which have the disadvantage of placing constraints on the design of the package that may preclude the product from meeting electrical performance requirements; B) Permanent stiffeners that are attached to the laminate around the perimeter, which have the disadvantage of being expensive, permanent, and have limited success in keeping the chipsite area flat; C) Temporary stiffeners also have the disadvantage of being expensive and difficult to remove, and can interfere with the standard manufacturing process; and D) Fixtures that rigidly constrain the laminate and have the disadvantage of not allowing for thermal expansions have limited effectiveness and interfere with standard processes.
It would therefore be desirable to provide an apparatus and method for constraining a laminate particularly along a vertical axis, while allowing for movement along a horizontal plane due to thermal expansion. It is further desirable to maintain a flat chip site area through a reflow processing step with minimal impact on the process, including cost and processing time to the manufacturing line.